When parallel data are sent between locations in digital systems, the associated clock signal is typically sent on a separate path. When both the data and clock signals arrive at the receiving location, the rising edge of the clock signal may be coincident with the rising edge of the data signals. It may be difficult to process the data signals at the receiving location with coincident rising edges. To overcome this difficulty, the data may be retimed by shifting the phase of the clock relative to the phase of the data.
Delay locked loops may be used to retime clock signals. However, delay locked loops may not be available in all development libraries. Additionally, delay locked loops may have high power consumption and constrictive operating parameters such as temperature range. A delay locked loop retiming circuit may also introduce jitter into the clock signal.